Education Background
Sep.1994-Jul. 1998 B.Sc Automatic Control, Nankai University
Sep.1998-Jul. 2004 Ph.D. Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences
Work Experience
Jan. 2005 - Nov. 2006 Post-doctor, Tsinghua University
Dec. 2006 - Present Faculty, National Research Center for Information Science and Technology, Tsinghua University
Academic Affiliations
Senior Member of China Computer Federation (CCF)
Executive Committee Member of the CCF Computer Architecture Technical Committee
Research Areas
Processor Hardware Security, Processor Architecture
Research Overview
(1) General Processor Vulnerability Fuzzing Platform
The platform employs modular code-block assembly to construct test case populations, integrates fine-grained runtime state monitoring for execution analysis, and utilizes vulnerability-driven anomaly detection models to enable automated, high-throughput black-box processor fuzzing. This approach not only detects known vulnerabilities and their variants but also discovered the previously unidentified Phantom (Leaky MDU) vulnerability. The findings were published at the Design Automation Conference (DAC). (2) Formal Verification Methodology for Processor Security
The methodology combines formal modeling of processor behaviors with rigorous definition of security properties, enabling systematic exploration of vulnerabilities including branch prediction vulnerabilities, micro-architectural data sampling vulnerabilities, and cache-based side-channel leakage. The framework demonstrated efficacy by uncovering a novel branch prediction variant, five previously undocumented cache side-channel exploitation techniques, and a cross-core attack targeting non-inclusive cache architectures. These findings were published in IEEE Transactions on Information Forensics and Security (TIFS) and the Asia and South Pacific Design Automation Conference (ASP-DAC).
(3) Secure Cache Architecture Design
The secure cache supporting up to 512 isolated partitions to mitigate cache side-channel attacks, was published in IEEE Transactions on Dependable and Secure Computing (TDSC).
Awards and Honors
(1) The scientific research achievement was selected into the Leading Scientific and Technological Achievements Collection at the World Internet Conference (Basic Research Category) (2023).
(2) First Prize of Shandong Provincial Science and Technology Progress Award (2022).
(3) First Prize of CCF Natural Science Award (2020).
(4)First Prize of China Electronics Society Science and Technology Progress Award (2020).
Academic Achievements
[1]. Lingfeng Yin, Haixia Wang, Yongqiang Lyu, Dongsheng Wang. VeriCache: Formally Verified Fine-Grained Partitioned Cache for Side-Channel-Secure Enclaves. IEEE Transactions on Dependable and Secure Computing, 2025: 1-12.
[2]. Shixuan Zhang, Haixia Wang, Pengfei Qiu, Yongqiang Lyu, Hongpeng Wang, Dongsheng Wang. SCAFinder: Formal Verification of Cache Fine-Grained Features for Side Channel Detection. IEEE Trans. Inf. Forensics Secur. 19: 8079-8093 (2024).
[3]. Rihui Sun,Pengfei Qiu,Yongqiang Lyu,Jian Dong,Haixia Wang,Dongsheng Wang,Gang Qu. Lightning: Leveraging DVFS-induced Transient Fault Injection to Attack Deep Learning Accelerator of GPUs. ACM Trans. Design Autom. Electr. Syst. 29(1): 14:1-14:22 (2024).
[4]. Chang Liu, Yongqiang Lyu, Haixia Wang, Pengfei Qiu, Dapeng Ju, Gang Qu, Dongsheng Wang. Leaky MDU: ARM Memory Disambiguation Unit Uncovered and Vulnerabilities Exposed. In Proceedings of the 60th Annual Design Automation Conference, 2023: 1-6.
[5]. Chang Liu, Yi Yang, Haoru Li, Pengfei Qiu, Yongqiang Lyu, Haixia Wang, Dapeng Ju, Dongsheng Wang. A survey of Branch Prediction Attacks on Modern Processors. Chinese Journal of Computers, 2022, 45(12): 2475-2509.
[6]. Zihan Xu, Lingfeng Yin, Yongqiang Lyu, Haixia Wang, Gang Qu, Dongsheng Wang. CacheGuard: A Behavior Model Checker for Cache Timing Side-Channel Security, 27th Asia and South Pacific Design Automation Conference, 2022 : 19-24.
[7]. Qian Ke, Chunlu Wang, Haixia Wang, Yongqiang Lyu, Zihan Xu, Dongsheng Wang:Model Checking for Microarchitectural Data Sampling Security. DSC 2022: 56-63.
[8]. Tongliang Li, Haixia Wang, Airan Shao, Dongsheng Wang. SSB-Tree: Making Persistent Memory B+-Trees Crash-Consistent and Concurrent by Lazy-Box. 36th IEEE International Parallel and Distributed Processing Symposium,2022: 70-80.
[9]. Shangming Cai, Dongsheng Wang, Haixia Wang, Yongqiang Lyu, Guangquan Xu, Xi Zheng, Athanasios V. Vasilakos: DynaComm: Accelerating Distributed CNN Training Between Edges and Clouds Through Dynamic Communication Scheduling. IEEE J. Sel. Areas Commun. 40(2): 611-625,2022.
[10]. Zizhong Wang, Tongliang Li, Haixia Wang, Airan Shao, Yunren Bai, Shangming Cai, Zihan Xu, Dongsheng Wang: CRaft: An Erasure-coding-supported Version of Raft for Reducing Storage Cost and Network Cost. FAST 2020: 297-308.
[11]. Shangming Cai, Dongsheng Wang, Zhanye Wang, Haixia Wang: CARD: A Congestion-Aware Request Dispatching Scheme for Replicated Metadata Server Cluster. ICPP 2020: 5:1-5:11.
[12]. Zizhong Wang, Haixia Wang, Airan Shao, Dongsheng Wang:An Adaptive Erasure-Coded Storage Scheme with an Efficient Code-Switching Algorithm. ICPP 2020: 35:1-35:11.
Yuchen Qiao, Kazuma Hashimoto, Akiko Eriguchi, Haixia Wang, Dongsheng Wang, Yoshimasa Tsuruoka, Kenjiro Taura: Parallelizing and optimizing neural Encoder-Decoder models without padding on multi-core architecture. Future Gener. Comput. Syst. 108: 1206-1213, 2020.
Talent Development
2023: Mentored students to win the Gold Award at the Huawei Kunpeng Application Innovation Competition.
2020: Advised students recognized with the Outstanding Master's Thesis Award from Tsinghua University and the Beijing Outstanding Graduate honor.
